Methods and apparatuses for instructions including a misprediction handling hint to reduce a branch misprediction penalty
AssigneeIntel Corporation
InventorHideki Ido
Life of this patent
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AssigneeIntel Corporation
InventorHideki Ido
Estimating the term…
Techniques for implementing a branch instruction having a misprediction handling hint to prevent instructions on a mispredicted path from getting cancelled are described. In certain examples, a hardware processor core includes a retirement circuit; a branch predictor circuit to predict a predicted path for a branch, and cause a speculative processing of the predicted path; a decode circuit to decode a single instruction into a decoded instruction, the single instruction having a field to indicate the retirement circuit is to allow retirement of the predicted path for the branch that is a misprediction; and an execution circuit to execute the decoded instruction to cause: the retirement circuit to allow the retirement of the predicted path that is the misprediction for the branch when the field is set to a first value, and the retirement circuit to disallow the retirement of the predicted path that is the misprediction for the branch when the field is otherwise.
An apparatus comprising:
A method comprising:
A non-transitory machine-readable medium that stores code that when executed by a machine, wherein the machine comprises a retirement circuit and a branch predictor circuit to predict a predicted path for a branch and cause a speculative processing of the predicted path, causes the machine to perform a method comprising:
Dependencies are inferred from the claim text.