Vector reverse

A processor comprising:

• an instruction fetch unit configured to receive a vector reverse instruction and a second instruction, wherein the vector reverse instruction specifies whether the processor is to perform the vector reverse instruction and the second instruction in parallel and further specifies that the vector reverse instruction is a single vector reverse operation;
• a register file that includes a source register configured to store a first vector that includes a set of elements and a destination register;
• a functional unit coupled to the register file and configured to, based on the vector reverse instruction:
• receive the first vector from the source register;
• reverse an order of the set of elements of the first vector to produce a second vector;
• and
• cause the second vector to be stored in the destination register, wherein the vector reverse instruction is completed in a single operation.

A method comprising:

• receiving a vector reverse instruction that specifies a source register from among a register file, a destination register from among the register file, and a functional unit from among a set of functional units, wherein the vector reverse instruction further specifies that the vector reverse instruction is single vector reverse operation;
• and
• based on the vector reverse instruction, performing, by the specified functional unit:
• receiving a first vector from the source register, wherein the first vector includes a set of elements;
• reversing the set of elements of the first vector to produce a second vector;
• and
• storing the second vector in the destination register,
• wherein the vector reverse instruction is completed in a single operation.