Systems and methods for shift last multiplication and accumulation (mac) process

A processing circuit, comprising:

• a first circuit block configured to:
• receive a first input, a second input, a third input, and a fourth input;
• perform multiplication on the first input and the second input to obtain a first partial product and a second partial product;
• perform multiplication on the third input and the fourth input to obtain a third partial product and a fourth partial product;
• sum the first partial product and the third partial product to obtain a first sum;
• and
• sum the second partial product and the fourth partial product to obtain a second sum;
• and
• a second circuit block configured to:
• receive the first sum and the second sum from the first circuit block;
• and
• generate an output by accumulating the first sum and the second sum.

A processing circuit, comprising:

• a first circuit block configured to:
• receive a first input, a second input, a third input, and a fourth input;
• multiply the first input by a first bit of the second input to obtain a first intermediate output;
• multiply the third input by a first bit of the fourth input to obtain a second intermediate output;
• sum the first intermediate output and the second intermediate output to obtain a first sum;
• multiply the first input by a second bit of the second input to obtain a third intermediate output;
• multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output;
• and
• sum the third intermediate output and the fourth intermediate output to obtain a second sum;
• and
• a second circuit block configured to:
• receive the first sum and the second sum from the first circuit block;
• and
• generate an output by accumulating the first sum and the second sum.