Sparsity-aware performance boost in compute-in-memory cores for deep neural network acceleration

A computing system comprising:

• a network controller;
• and
• a processor coupled to the network controller, wherein the processor includes logic coupled to one or more substrates, the logic including:
• a compute-in-memory (CiM) enabled memory array to conduct digital bit-serial multiply and accumulate (MAC) operations on multi-bit input data and weight data stored in the CiM enabled memory array,
• an adder tree coupled to the CiM enabled memory array,
• a left shift stage coupled to the CiM enabled memory array and the adder tree,
• an accumulator coupled to the adder tree, and
• an input bit selection stage coupled to the CiM enabled memory array, the input bit selection stage to restrict serial bit selection on the multi-bit input data to non-zero values during the digital MAC operations.