Combined sparse and block floating arithmetic

Abstract

A processing device for encoding floating point numbers comprising memory configured to store data comprising the floating point numbers and circuitry. The circuitry is configured to, for a set of the floating point numbers, identify which of the floating point numbers represent a zero value and which of the floating point numbers represent a non-zero value, convert the floating point numbers which represent a non-zero value into a block floating point format value and generate an encoded sparse block floating point format value. The circuitry is also configured to, decode floating point numbers. For an encoded block floating point format value, the circuitry converts the encoded block floating point format value to a set of non-zero floating point numbers based on a sparsity mask previously generated to encode the encoded block floating point format value and generates a non-sparse set of floating point values.

Dependencies are inferred from the claim text.