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US 2024/0201891 A1Published application
Input voltage degradation detection
AssigneeMicron Technology, Inc.
InventorsJoseph A. Oberle, David C. Sastry, Anil Kumar Agarwal, Sumit Tayal
Life of this patent
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Abstract
A method includes performing a host-initiated test memory operation of a memory device in a memory sub-system and detecting, via a sensor circuit, an input voltage or input current of the memory device or the memory sub-system. The method further includes determining whether the input voltage or the input current meets a degradation criteria and generating a management control signal responsive based on the determination whether the input voltage or the input current meets the degradation criteria.
Claims20
A method comprising:
- performing a host-initiated test memory operation of a memory device in a memory sub-system;
- detecting, via a sensor circuit, an input voltage or input current of the memory device or the memory sub-system;
- determining whether the input voltage or the input current meets a degradation criteria;
- and
- generating a management control signal based on the determination whether the input voltage or the input current meets the degradation criteria.
2 more elements
An apparatus comprising:
- a memory sub-system including a memory device, a sensor circuit, and a memory controller, the memory controller configured to:
- receive, via a sensor circuit, an input voltage or an input current of the memory device or the memory sub-system during performance of a host-initiated test memory operation of the memory device;
- determine whether the detected input voltage or the input current meets a first degradation criteria;
- responsive to a determination that the detected input voltage or the input current does not meet the first degradation criteria, generate a management control signal;
- responsive to a determination that the detected input voltage or the input current meets the first degradation criteria, determine whether the detected input voltage or the input current meets a second degradation criteria;
- determine whether the detected input voltage or the input current meets the second degradation criteria;
- and
- responsive to a determination that the detected input voltage or the input current meets the second degradation criteria, generate the management control signal.
5 more elements
A system comprising:
- a memory sub-system including a memory device;
- a sensor circuit;
- and
- a memory controller configured to:
- receive, via a sensor circuit, an input voltage of the memory device or the memory sub-system during performance of a host-initiated test memory operation of the memory device;
- determine whether the input voltage meets a first degradation criteria;
- responsive to a determination that the input voltage does not meet the first degradation criteria, generate a management control signal to cause:
- a counter to increment;
- and
- storage of the input voltage of the memory device or the memory sub-system;
- responsive to a determination that the input voltage meets the first degradation criteria, determine whether the input voltage meets a second degradation criteria;
- determine whether the input voltage meets the second degradation criteria;
- and
- responsive to a determination that the input voltage meets the second degradation criteria, generate a management control signal to cause:
- the counter to increment;
- and
- storage of the input voltage of the memory device or the memory sub-system.
14 more elements
Dependencies are inferred from the claim text.