Row address latching for multiple activate command protocol

A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

• receive a first activate command that indicates first values for a first set of bits of a row address;
• receive a second activate command that indicates first values for a second set of bits of the row address;
• receive a third activate command indicating second values for the first set of bits of the row address;
• and
• activate a page of memory using the first values for the first set of bits and the first values for the second set of bits, wherein the activation of the page is performed based at least in part on reception of the second activate command, and occurs after reception of the third activate command.

An apparatus, comprising:

• one or more memories storing processor-executable code;
• and
• one or more processors coupled with the one or more memories and operable to execute the code to cause the apparatus to:
• receive a first activate command that indicates first values for a first set of bits of a row address;
• receive a second activate command that indicates first values for a second set of bits of the row address;
• receive a third activate command indicating second values for the first set of bits of the row address;
• and
• activate a page of memory using the first values for the first set of bits and the first values for the second set of bits, wherein activating the page occurs after receiving the third activate command.