System with mcu and flash memory and control method for deep power down control thereof
AssigneeGigadevice Semiconductor Inc.
InventorYang GAO
Life of this patent
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Abstract
The present invention provides a system with an MCU and flash memory and a method for DPD control thereof. A new DPD mode (first DPD mode) is provided by simply adding a power supply pin to the MCU. The power supply pin is coupled to a power supply terminal of the flash memory. In a deep power down mode, the flash memory is configured to be entirely powered down, leading to even lower system power consumption than in a conventional DPD mode (second DPD mode).
Claims20
A system with a microcontroller unit (MCU) and a flash memory, wherein the flash memory is configured to store codes and/or data for the MCU and comprises a first circuit portion and a second circuit portion, and wherein the MCU comprises at least one power supply pin coupled to a power supply terminal of the flash memory,
- wherein, in a normal mode, the MCU is configured to utilize a power supply control signal to enable power to be supplied to the power supply terminal of the flash memory, thereby allowing a normal operation of each of the first and second circuit portions;
- and in a first deep power down (DPD) mode, the MCU is configured to utilize the power supply control signal to cut off power to the power supply terminal of the flash memory, thereby powering down each of the first and second circuit portions.
A method for deep power down (DPD) control of a system with a microcontroller unit (MCU) and a flash memory, wherein the flash memory is configured to store codes and/or data for the MCU and comprises a first circuit portion and a second circuit portion;
- the MCU comprises at least one power supply pin coupled to a power supply terminal of the flash memory;
- and the method comprises:
- when entry of the system into a deep sleep mode is required, the MCU is configured to utilize a power supply control signal to cut off power to the power supply terminal of the flash memory, enabling the flash memory to enter a first DPD mode in which each of the first and second circuit portions is powered down.
Dependencies are inferred from the claim text.