Input-output memory management unit with memory protection
AssigneeMediatek Inc.
InventorsYu-Tien Chang, Lin-Ming Hsu, Chun-Ming Chou
Life of this patent
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AssigneeMediatek Inc.
InventorsYu-Tien Chang, Lin-Ming Hsu, Chun-Ming Chou
Estimating the term…
A system on chip includes a dynamic random access memory (DRAM) controller, a secure range (SR) permission checker, a plurality of intellectual property (IP) cores. The DRAM controller includes a SR table configured to store a start address, an end address, and enabled registers of each SR and an access identification (AID) permission table configured to store access permissions of SRs of each AID. The SR permission checker is embedded in the DRAM controller or a bus and linked to the SR table and the AID permission table, and configured to check the access permissions of the SRs according to the AID permission table. The plurality of IP cores linked to the DRAM controller, and comprising a translation lookaside buffer (TLB) comprising an input-output memory management unit (IOMMU) table or an input-output memory protection unit (IOMPU) table to store SR information.
A system on chip, comprising:
A computing device, comprising:
A method for controlling access permissions to a memory, comprising:
Dependencies are inferred from the claim text.