Semiconductor memory device and memory system including the same

A method of operating a memory system that includes a semiconductor memory device and a memory controller configured to communicate with the semiconductor memory device and configured to control the semiconductor memory device, wherein the semiconductor memory device includes a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines, a first cyclic redundancy check (CRC) engine and an on-die error correction code (ECC) engine, the method comprising:

• detecting, by the first CRC engine, an error in a main data and a system parity data received from the memory controller through a link;
• generating, by the CRC engine, a first error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data;
• performing, by the on-die ECC engine, an ECC encoding operation on the main data and the system parity data;
• and
• performing, by the on-die ECC engine, an ECC decoding operation on the main data and the system parity data to correct a correctable error in the main data.

The method of 13, during a write operation on the semiconductor memory device, further comprising:

• generating, by a second CRC engine in the memory controller, the system parity data based on the main data;
• transmitting, by the second CRC engine, the main data and the system parity data to the semiconductor memory device;
• generating, by the first CRC engine, a first reference system parity data based on the main data;
• and
• transmitting, by the first CRC engine, to the memory controller, the first error flag having a first logic level indicating that the first type of error occurs based on comparing the system parity data with the first reference system parity data.

A method of operating a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines, a cyclic redundancy check (CRC) engine and an on-die error correction code (ECC) engine, the method comprising:

• detecting, by the CRC engine, an error in a main data and a system parity data received from a memory controller through a link, the memory controller being external to the semiconductor memory device;
• generating, by the CRC engine, an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data;
• performing, by the on-die ECC engine, an ECC encoding operation on the main data and the system parity data;
• performing, by the on-die ECC engine, an ECC decoding operation on the main data and the system parity data;
• generating, by the CRC engine, a first reference system parity data based on the main data provided from the memory controller;
• and
• determining, by the CRC engine, a logic level of the error flag associated with one of the first type of error or the second type of error based on comparison of the system parity data and the first reference system parity data.