Single event upset tolerant memory device

A semiconductor memory device comprising:

• a first array of semiconductor memory cells arranged in rows and columns, each memory cell including a pair of access transistors that are coupled to a data storage cell of the memory cell;
• a second array of semiconductor memory cells arranged in rows and columns, each memory cell including a pair of access transistors that are coupled to a data storage cell of the memory cell, the columns of the first array of semiconductor memory cells aligned with the columns of the second array of semiconductor memory cells, wherein bit lines coupled to the first array of semiconductor memory cells extend over the second array of semiconductor memory cells;
• a plurality of sense amplifiers configured to read data states from the first array of memory cells and the second array of memory cells, the plurality of sense amplifiers configured to output a word based on the read data states of the first and second arrays of semiconductor memory cells, the first and second arrays of semiconductor memory cells disposed on a common side of the plurality of sense amplifiers;
• and
• a first plurality of high ratio column MUXES connecting bit lines of the first array of memory cells and the second array of memory cells to the plurality of sense amplifiers.

A semiconductor memory device comprising:

• a first array of semiconductor memory cells arranged in rows and columns, each memory cell including a pair of access transistors that are coupled to a data storage cell of the memory cell;
• a second array of semiconductor memory cells arranged in rows and columns, each memory cell including a pair of access transistors that are coupled to a data storage cell of the memory cell, the columns of the first array of semiconductor memory cells aligned with the columns of the second array of semiconductor memory cells, wherein bit lines coupled to the first array of semiconductor memory cells extend over the second array of semiconductor memory cells;
• a plurality of sense amplifiers configured to read data states from the first array of memory cells and the second array of memory cells, the plurality of sense amplifiers configured to output a word based on the read data states of the first and second arrays of semiconductor memory cells, the first and second arrays of semiconductor memory cells disposed on a common side of the plurality of sense amplifiers, the sense amplifiers configured to selectively output a WORD having 9 bits when operating one of the first or second arrays, and to output a WORD having 18 bits by operating both of the first or second arrays;
• a first plurality of 8:1 column MUXES connecting bit lines of the first array of memory cells and the second array of memory cells to the plurality of sense amplifiers;
• and
• wherein semiconductor memory cells aligned in a first column spanning the first array and the second array are formed on one of a P or N-doped region of a substrate in the first array, and the other of the P or N-doped region of the substrate in the second array.