Decoding method, memory storage device and memory control circuit unit

A memory storage device, comprising:

• a connection interface unit configured to be coupled to a host system;
• a rewritable non-volatile memory module;
• and
• a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to:
• send at least one read command sequence, wherein the at least one read command sequence instructs to read a first physical unit in the rewritable non-volatile memory module;
• receive response data from the rewritable non-volatile memory module, wherein the response data comprises a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process;
• determine a decoding parameter corresponding to the first memory cell according to the plurality of identification bits;
• and
• decode data read from the first memory cell according to the decoding parameter.

A memory control circuit unit, configured to control a rewritable non-volatile memory module, the memory control circuit unit comprising:

• a host interface configured to be coupled to a host system;
• a memory interface configured to be coupled to the rewritable non-volatile memory module;
• an error detecting and correcting circuit;
• and
• a memory management circuit coupled to the host interface, the memory interface, and the error detecting and correcting circuit,
• wherein the memory management circuit is configured to:
• send at least one read command sequence, wherein the at least one read command sequence instructs to read a first physical unit in the rewritable non-volatile memory module;
• receive response data from the rewritable non-volatile memory module, wherein the response data comprises a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process;
• and
• determine a decoding parameter corresponding to the first memory cell according to the plurality of identification bits, and
• the error detecting and correcting circuit is configured to decode data read from the first memory cell according to the decoding parameter.