SSD with Reference Clock Loss Tolerant Oscillator

A storage device, comprising:

• a memory die;
• and
• an oscillator circuit configured to:
• generate a clock based on a host reference clock, and
• output an output clock to the memory die;
• wherein while the host reference clock is available, a positive edge of the output clock is aligned in time with a positive edge of the host reference clock and a negative edge of the output clock is aligned in time with a negative edge of the generated clock during a respective clock cycle of the host reference clock, and in response to loss of the host reference clock, a positive edge of the output clock is aligned in time with a positive edge of the generated clock within a generated clock cycle following the loss.

A storage device, comprising:

• a memory die;
• and
• an oscillator circuit configured to:
• generate a clock based on a host reference clock, and
• output an output clock to the memory die;
• wherein while the host reference clock is available, the oscillator circuit is configured to output the output clock at a frequency that is identical to a frequency of the host reference clock or a division factor of the frequency of the host reference clock,
• in response to loss of the host reference clock, the oscillator circuit is configured to reduce the frequency of the output clock to a frequency of the generated clock within a generated clock cycle following the loss, and
• in response to re-availability of the host reference clock, the oscillator circuit is configured to increase the frequency of the output clock back to the frequency of the host reference clock within a plurality of host reference clock cycles following the re-availability.