Processor synchronization systems and methods
AssigneeMicrosoft Technology Licensing, LLC
InventorsCharles Walter BOECKER, Piyush Abhay HATOLKAR, Asad AZAM, Maya SUBHADRA
Life of this patent
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Abstract
Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.
Claims20
A synchronization system comprising:
- a first integrated circuit die comprising:
- one or more first digital processors;
- a synchronization circuit;
- and
- a first clock generator;
- and
- one or more second integrated circuit die comprising:
- one or more second digital processors;
- and
- a second clock generator,
- wherein the synchronization circuit receives count phases from the first and second integrated circuit die and adjusts delay lines in the first and second clock generators to synchronize clock signals to first and second digital processors.
A method of synchronizing processors comprising:
- generating clock signals to one or more digital processors on a plurality of integrated circuit die when a plurality of phase locked loops on the plurality of integrated circuit die are locked to a reference clock;
- measuring, by a first integrated circuit die of the plurality of integrated circuit die, count phases from the plurality of integrated circuit die;
- and
- adjusting, by the first integrated circuit die, delay lines on the plurality of integrated circuit die to adjust the clock signals to synchronize clock signals to the one or more digital processors on the plurality of integrated circuit die.
A synchronization system comprising:
- means for generating clock signals to one or more digital processors on a plurality of integrated circuit die when a plurality of phase locked loops on the plurality of integrated circuit die are locked to a reference clock;
- means for measuring count phases from the plurality of integrated circuit die;
- and
- means for adjusting delay lines on the plurality of integrated circuit die to adjust the clock signals to synchronize clock signals to the one or more digital processors on the plurality of integrated circuit die.
Dependencies are inferred from the claim text.