Liquid crystal panel and method for manufacturing liquid crystal display device

A liquid crystal panel comprising:

• an active matrix substrate;
• a counter substrate;
• and
• a liquid crystal layer sandwiched between the active matrix substrate and the counter substrate,
• wherein the active matrix substrate includes
• a substrate having a principal surface including a display region, a non-display region located around the display region, and a testing terminal region located outside and adjacent to the non-display region,
• a plurality of source bus lines each disposed in the display region of the substrate, the plurality of source bus lines extending in a first direction,
• a plurality of gate bus lines each disposed in the display region of the substrate, the plurality of gate bus extending in a second direction intersecting the first direction,
• a plurality of pixels disposed in the display region of the substrate, the pixels including TFTs each connected to one of the plurality of source bus lines and one of the plurality of gate bus lines,
• a first out-panel testing terminal disposed in the testing terminal region of the substrate,
• a second out-panel testing terminal disposed in the testing terminal region of the substrate,
• a second in-panel testing terminal disposed in the non-display region of the substrate,
• a third in-panel testing terminal disposed in the non-display region of the substrate,
• a gate driver circuit disposed in the non-display region of the substrate and connected to the plurality of gate bus lines and the second out-panel testing terminal,
• a gate switch circuit disposed in the non-display region of the substrate and connected to the plurality of gate bus lines and the second in-panel testing terminal, the gate switch circuit outputting a control signal to the plurality of gate bus lines in accordance with a signal that is inputted from the second in-panel testing terminal,
• a demultiplexer circuit disposed in the non-display region of the substrate and connected to the plurality of source bus lines and the first out-panel testing terminal, and
• a source switch circuit disposed in the non-display region of the substrate and connected to the plurality of source bus lines and the third in-panel testing terminal, the source switch circuit applying a predetermined voltage to the plurality of source bus lines in accordance with a signal that is inputted from the third in-panel testing terminal.