Method and system for fabricating a mems device cap
AssigneeInvenSense, Inc.
InventorCamillo Pilla
Life of this patent
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Abstract
A device includes a first die and a second die. The first die and the second die are stacked and form a monolithic die. A first side of the first die faces a first side of the second die. The second die comprises an electrical connection within its periphery and on a side other than the first side of the second die. The electrical connection exposes the second die to an environment outside of the monolithic die. The electrical connection is configured to facilitate electrical connection between the second die of the monolithic die and an electronic component that is external to the monolithic die.
Claims20
A method comprising:
- forming a plurality of complementary metal oxide semiconductor (CMOS) dice on a CMOS wafer, wherein each CMOS die of the plurality of CMOS dice includes a plurality of through silicon vias (TSVs) associated therewith and positioned on a periphery of its associated CMOS die;
- forming a plurality of micro-electro-mechanical systems (MEMS) dice on a MEMS wafer;
- forming a monolithic wafer by stacking the CMOS wafer and the MEMS wafer, wherein the monolithic wafer comprises a plurality of monolithic dice, wherein each monolithic die of the plurality of monolithic dice comprises a CMOS die and a MEMS die that are stacked on top of one another forming a monolithic die;
- and
- separating a first monolithic die from a second monolithic die of the monolithic wafer by cutting through a scribe region between the first monolithic die and the second monolithic die,
- wherein the first monolithic die comprises a first MEMS die and a first CMOS die and wherein the second monolithic die comprises a second MEMS die and a second CMOS die,
- wherein the separating exposes at least one or more TSVs of the plurality of TSVs of the first CMOS die to an environment outside of the first monolithic die,
- wherein the separating exposes at least one or more TSVs of the plurality of TSVs of the second CMOS die to the environment outside of the second monolithic die,
- wherein the at least one or more TSVs of the plurality of TSVs of the first CMOS is configured to facilitate electrical connection between the first CMOS die of the first monolithic die and an electronic component that is external to the first monolithic die.
A device comprising:
- a first die;
- and
- a second die,
- wherein the first die and the second die are stacked and form a monolithic die, wherein a first side of the first die faces a first side of the second die,
- wherein the second die comprises an electrical connection within its periphery and on a side other than the first side of the second die, wherein the electrical connection exposes the second die to an environment outside of the monolithic die, and wherein the electrical connection is configured to facilitate electrical connection between the second die of the monolithic die and an electronic component that is external to the monolithic die.
A monolithic device comprising:
- a micro-electro-mechanical systems (MEMS) die;
- and
- a complementary metal oxide semiconductor (CMOS) die bonded to the MEMS die forming a single integrated die,
- wherein the CMOS die comprises a plurality of through silicon vias (TSVs) positioned on an outer edge of the CMOS die and is exposed to an environment outside of the single integrated die, and
- wherein the plurality of TSVs is configured to facilitate electrical connection between the CMOS die and an electronic component that is external to the single integrated die.
Dependencies are inferred from the claim text.