Memory device using semiconductor element

A memory device that uses a semiconductor element, the memory device comprising:

• a substrate;
• a first semiconductor layer placed on the substrate;
• a first impurity layer placed on part of a surface of the first semiconductor layer;
• a second impurity layer extending in a vertical direction by being placed in contact with the first impurity layer;
• a second semiconductor layer extending in the vertical direction by being placed in contact with a columnar part of the second impurity layer;
• a first insulating layer covering part of the first semiconductor layer and part of the second impurity layer;
• a first gate insulating layer surrounding the second impurity layer and the second semiconductor layer by being placed in contact with the first insulating layer;
• a first gate conductor layer placed in contact with the first insulating layer and the first gate insulating layer;
• a second insulating layer formed in contact with the first gate conductor layer and the first gate insulating layer;
• a third semiconductor layer placed in contact with the second semiconductor layer;
• a second gate insulating layer partially or entirely surrounding an upper part of the third semiconductor layer;
• a second gate conductor layer partially or entirely covering an upper part of the second gate insulating layer;
• a third impurity layer and a fourth impurity layer placed in contact with a lateral surface of the third semiconductor layer located on an outer side of one end of the second gate conductor layer in a horizontal direction in which the third semiconductor layer extends;
• a first interconnecting conductor layer connected to the third impurity layer;
• a second interconnecting conductor layer connected to the fourth impurity layer;
• a third interconnecting conductor layer connected to the second gate conductor layer;
• a fourth interconnecting conductor layer connected to the first gate conductor layer;
• and
• a fifth interconnecting conductor layer connected to the first impurity layer,
• wherein a memory write operation is performed by controlling voltages applied to the first interconnecting conductor layer, the second interconnecting conductor layer, the third interconnecting conductor layer, the fourth interconnecting conductor layer, and the fifth interconnecting conductor layer and performing an operation of generating electron groups and positive hole groups in the third semiconductor layer and the second semiconductor layer, by an impact ionization phenomenon or a gate induced drain leakage current using a current passed between the third impurity layer and the fourth impurity layer, an operation of removing the generated electron groups or positive hole groups whichever are minority carriers in the third semiconductor layer and the second semiconductor layer, and an operation of causing part or all of the electron groups or positive hole groups whichever are majority carriers in the third semiconductor layer and the second semiconductor layer to remain in the third semiconductor layer and the second semiconductor layer, and
• a memory erase operation is performed by controlling voltages applied to the first interconnecting conductor layer, the second interconnecting conductor layer, the third interconnecting conductor layer, the fourth interconnecting conductor layer, and the fifth interconnecting conductor layer, and extracting the electron groups or the positive hole groups whichever are majority carriers remaining in the second semiconductor layer or the third semiconductor layer from at least one location in the first impurity layer, the second impurity layer, the third impurity layer, and the fourth impurity layer by recombining the electron groups or the positive hole groups with majority carriers in the first impurity layer, the second impurity layer, the third impurity layer, and the fourth impurity layer.