Deadlock prevention of switch memory overflow
AssigneeNokia Solutions and Networks Oy
InventorAndrea Enrici
Life of this patent
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Abstract
Example embodiments disclose a method for avoiding deadlock in a network includes generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches, analyzing the finite state machine, determining at least one memory overflow state based on the analyzing, generating at least one anti-deadlock rule in response to determining the at least one memory overflow state, and transmitting the at least one anti-deadlock rule to the plurality of switches.
Claims20
A method for avoiding deadlock in a network, the method comprising:
- generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches;
- analyzing the finite state machine;
- determining at least one memory overflow state based on the analyzing;
- generating at least one anti-deadlock rule in response to determining the at least one memory overflow state;
- and
- transmitting the at least one anti-deadlock rule to the plurality of switches.
An apparatus for avoiding deadlock in a network, the apparatus comprising:
- a memory;
- and
- processing circuitry configured to cause the apparatus to
- generate a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches,
- analyze the finite state machine,
- determine at least one memory overflow state based on the analysis,
- generate at least one anti-deadlock rule in response to determining the at least one memory overflow state, and
- transmit the at least one anti-deadlock rule to the plurality of switches.
A method for avoiding deadlock in a network, the method comprising:
- routing, by a switch of a plurality of switches, a data packet according to at least one anti-deadlock rule, the at least one anti-deadlock rule based on a deadlock path within the network, the deadlock path in the network based on at least one memory overflow state determined by an analysis of a finite state machine.
Dependencies are inferred from the claim text.