Voltage multiple circuit

An integrated circuit, comprising:

• an input node configured to receive an input voltage;
• an output node configured to be coupled to an output capacitor and configured to produce an output voltage higher than the input voltage;
• a first input control node configured to receive a first clock signal;
• a second input control node configured to receive a second clock signal, the second clock signal being in phase opposition to the first clock signal, wherein the integrated circuit switches between a first commutation state and a second commutation state as a function of the first and second clock signals;
• an ordered sequence of intermediate voltage nodes arranged between the input node and the output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes;
• a respective capacitor coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is configured to be selectively couplable to the input node;
• a respective capacitor coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node;
• a respective capacitor coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence;
• a respective capacitor coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence;
• and
• a first plurality of selectively conductive electronic components coupled to the intermediate voltage nodes of the ordered sequence, the first plurality of selectively conductive electronic components comprising transistors arranged in a string between the input node and the output node, the intermediate voltage nodes located between subsequent transistors of the string,
• wherein, in the first commutation state, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the output node, and
• wherein, in the second commutation state, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.

A method, comprising:

• receiving, at an input node of a voltage multiplier circuit, an input voltage;
• generating, at an output node of the voltage multiplier circuit, an output voltage, the output node coupled to an output capacitor, the output voltage being higher than the input voltage, wherein an ordered sequence of intermediate voltage nodes is arranged between the input node and the output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes, wherein a respective capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence, wherein a respective capacitor is coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence, and wherein a first plurality of selectively conductive electronic components is coupled to the intermediate voltage nodes of the ordered sequence;
• receiving a first clock signal at a first input control node, wherein a respective capacitor is coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is selectively couplable to the input node;
• receiving a second clock signal at a second input control node, the second clock signal being in phase opposition to the first clock signal, wherein a respective capacitor is coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node;
• switching between a first commutation state and a second commutation state based on the first and second clock signals;
• in the first commutation state, providing, using the first plurality of selectively conductive electronic components, electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the output node, the first plurality of selectively conductive electronic components comprising transistors arranged in a string between the input node and the output node, the intermediate voltage nodes located between subsequent transistors of the string;
• and
• in the second commutation state, providing, using the first plurality of selectively conductive electronic components, electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.