Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a first active pattern on a substrate and a second active pattern on the substrate, each of the first and second active patterns including a first region having a first width, a second region having a second width less than the first width, and a third region between the first region and the second region;
• a first source/drain pattern on the third region of the first active pattern and a first channel pattern on the third region of the first active pattern;
• a second source/drain pattern on the third region of the second active pattern and a second channel pattern on the third region of the second active pattern;
• and
• a gate electrode on the first channel pattern and the second channel pattern, wherein
• the gate electrode extends in a first direction from the second active pattern to the first active pattern,
• the third region of the first active pattern has a recessed sidewall of a concave profile, and
• the third region of the second active pattern has an inclined sidewall of a convex profile.

A semiconductor device, comprising:

• an active pattern on a substrate;
• a device isolation layer that at least partly fills a trench defining the active pattern;
• a source/drain pattern on the active pattern;
• a channel pattern on the active pattern and connected to the source/drain pattern, the channel pattern including a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other;
• a gate electrode on the channel pattern, the gate electrode extending in a first direction and including a plurality of inner electrodes between the plurality of semiconductor patterns and an outer electrode on the plurality of semiconductor patterns;
• a gate dielectric layer between the gate electrode and the channel pattern;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer dielectric layer on the gate capping pattern;
• an active contact that penetrates the interlayer dielectric layer to come into electrical connection with the source/drain pattern;
• a metal-semiconductor compound layer between the active contact and the source/drain pattern;
• a gate contact that penetrates the interlayer dielectric layer and the gate capping pattern and comes into electrical connection with the gate electrode;
• a first metal layer on the interlayer dielectric layer, the first metal layer including a plurality of first wiring lines that are correspondingly electrically connected to the active contact and the gate contact;
• and
• a second metal layer on the first metal layer, wherein
• the second metal layer includes a plurality of second wiring lines electrically connected to the first metal layer,
• the active pattern includes a first region having a first width, a second region having a second width less than the first width, and a third region between the first region and the second region, and
• a third width of the third region decreases and then increases in a direction from the first region toward the second region.