Semiconductor package

A semiconductor package comprising:

• a lower chip;
• a chip stacked structure arranged on the lower chip, the chip stacked structure comprising a plurality of upper chips;
• an underfill layer disposed between the lower chip and the chip stacked structure and between the plurality of upper chips;
• and
• a molding layer surrounding the underfill layer and the chip stacked structure,
• wherein the lower chip has at least one lower trench positioned on an upper surface of the lower chip,
• a portion of the at least one lower trench overlaps the molding layer in a vertical direction, and a remaining portion of the at least one lower trench overlaps the underfill layer in the vertical direction, and
• the portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer, and the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer.

A semiconductor package comprising:

• a package substrate;
• a redistribution structure arranged on the package substrate;
• a sub-semiconductor package arranged on the redistribution structure;
• and
• a semiconductor chip arranged on the redistribution structure and spaced apart from the sub-semiconductor package in a horizontal direction,
• wherein the sub-semiconductor package comprises a lower chip, a chip stacked structure arranged on the lower chip, the chip stacked structure comprising a plurality of upper chips, an underfill layer disposed between the lower chip and the chip stacked structure and between the plurality of upper chips, and a molding layer surrounding the underfill layer and the chip stacked structure,
• wherein the lower chip has at least one lower trench positioned on an upper surface of the lower chip, and at least one of the plurality of upper chips has at least one upper trench positioned on an upper surface of the at least one of the plurality of upper chips.