US 2024/0194260 A1 · MEMORY DEVICE STRUCTURE AND FABRICATION METHOD

Abstract

A method for forming a 3D memory device includes forming an array wafer having a memory array layer and a CMOS layer stacked together, including: forming the CMOS layer having HV circuitry of a plurality of peripheral devices, and forming a plurality of memory cells and a string structure in the memory array layer. The memory array layer includes at least one cell region for forming the memory cells and at least one string structure region for forming the string structure, and the CMOS layer includes at least one string driver region. The method also includes forming a CMOS wafer having LV circuitry and LLV circuitry of the plurality of peripheral devices, the CMOS wafer including at least one page buffer region; bonding the array wafer and the CMOS wafer at a bonding interface; and forming the 3D memory device based on the bonded array wafer and CMOS wafer.

Claims20

Dependent claims

A method for forming a three-dimensional (3D) memory device, comprising:

forming an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, including:
forming the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and forming a plurality of memory cells and a string structure in the memory array layer, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one string structure region for forming the string structure, and the CMOS layer includes at least one string driver region;
forming a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region;
bonding the array wafer and the CMOS wafer at a bonding interface;
and
forming the 3D memory device based on the bonded array wafer and CMOS wafer.

3 more elements

A three-dimensional (3D) memory device, comprising:

an array wafer having a memory array layer and a complementary metal-oxide-semiconductor (CMOS) layer stacked together, the CMOS layer having high-voltage (HV) circuitry of a plurality of peripheral devices, and the memory array layer having a plurality of memory cells and a string structure, wherein the memory array layer includes at least one cell region for forming the memory cells and at least one string structure region for forming the string structure, and the CMOS layer includes at least one string driver region;
and
a CMOS wafer having low-voltage (LV) circuitry and low-low-voltage (LLV) circuitry of the plurality of peripheral devices, wherein the CMOS wafer includes at least one page buffer region,
wherein the array wafer and the CMOS wafer are bonded at a bonding interface.

1 more element

Dependencies are inferred from the claim text.

Memory device structure and fabrication method

Life of this patent

Memory device structure and fabrication method

Life of this patent

Abstract

Claims20