Apparatuses and methods for a multi-bit duty cycle monitor

An apparatus comprising:

• a memory configured to perform access operations based, at least in part, on a clock signal;
• a duty cycle adjuster configured to adjust the duty cycle of the clock signal based on a duty code;
• and
• a duty cycle monitor coupled to the adjusted clock signal and configured to provide a multi-bit signal with a state responsive to the duty cycle of the adjusted clock signal,
• wherein the state of the multi-bit signal is updated while the access operations are being performed, and wherein the duty code is increased responsive to the multi-bit signal being in a first state, and decreased responsive to the multi-bit signal being in a second state.

A method comprising:

• performing access operations on a memory device, wherein timing of the access operations is based, at least in part, on a clock signal;
• adjusting a duty cycle of the clock signal based on a duty code;
• and
• generating, while performing the access operations, a signal which indicates a direction of adjustment to the duty code based at least in part on the duty cycle of the clock signal and a target duty cycle value.

An apparatus comprising:

• a memory device configured to perform access operations based, at least in part, on a clock signal;
• a first comparator configured to provide a first output with a value based on a duty cycle of the clock signal being above an upper threshold;
• a second comparator configured to provide a second output with a value based on the duty cycle of the clock signal being above or below a target duty cycle;
• a third comparator configured to provide a third output with a value based on the duty cycle of the clock signal being below a lower threshold;
• and
• a mode register configured to store a state of a multi-bit signal, wherein the state of the multi-bit signal is based on the first output, the second output, and the third output.