Gate driver and display device using the same

A gate driver comprising

• a plurality of signal transmitters connected in a cascaded manner via a carry line through which a carry signal is applied to a signal transmitter from a previous signal transmitter,
• wherein an nth signal transmitter of the plurality of signal transmitters includes:
• a first output circuit configured to output a carry signal to a first output node based on a voltage at a first control node and a voltage at a second control node;
• and
• a second output circuit configured to output a gate signal to a second output node based on the voltage at the first control node and the voltage at the second control node,
• wherein the first output circuit includes:
• a pull-up transistor configured to apply a gate high voltage to the first output node in response to a charging voltage at the first control node;
• a pull-down transistor configured to apply a gate low voltage to the first output node in response to a charging voltage at the second control node;
• a first capacitor connected between a gate of the pull-up transistor and the first output node;
• and
• a second capacitor connected between the first output node and a low-potential voltage line,
• where n is a positive integer.

A display device comprising:

• a display panel in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are disposed;
• a data driver configured to supply a data voltage of pixel data to the data lines;
• and
• a gate driver configured to supply a gate signal to the gate lines,
• wherein the gate driver includes a plurality of signal transmitters connected in a cascaded manner via a carry line through which a carry signal is applied to a signal transmitter from a previous signal transmitter,
• wherein an nth signal transmitter of the plurality of signal transmitters includes:
• a first output circuit configured to output a carry signal to a first output node based on a voltage at a first control node and a voltage at a second control node;
• a second output circuit configured to output a boosting signal to a second output node based on the voltage at the first control node and the voltage of the second control node;
• and
• a third output circuit configured to output a gate signal to a third output node based on the voltage at the first control node and the voltage at the second control node,
• wherein the second output circuit includes:
• a pull-up transistor configured to apply a gate high voltage to the second output node in response to a charging voltage at the first control node;
• a pull-down transistor configured to apply a gate low voltage to the second output node in response to a charging voltage at the second control node;
• and
• a first capacitor connected between a gate of the pull-up transistor and the second output node.

A display device comprising:

• a display panel in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are disposed;
• a data driver configured to supply a data voltage of pixel data to the data lines;
• and
• a gate driver configured to supply a gate signal to the gate lines,
• wherein the gate driver includes a plurality of signal transmitters connected in a cascaded manner via a carry line through which a carry signal is applied to a signal transmitter from a previous signal transmitter,
• wherein an nth signal transmitter of the plurality of signal transmitters includes:
• a first output circuit configured to output a carry signal to a first output node based on a voltage at a first control node that pulls up an output voltage at the first output node and a voltage at a second control node that pulls down the output voltage;
• and
• a second output circuit configured to output a gate signal to a second output node based on the voltage at the first control node and the voltage at the second control node,
• wherein the first output circuit includes:
• a pull-up transistor configured to apply a gate high voltage to the first output node in response to a charging voltage at the first control node;
• a pull-down transistor configured to apply a gate low voltage to the first output node in response to a charging voltage at the second control node;
• a first capacitor connected between a gate of the pull-up transistor and the first output node;
• and
• a second capacitor connected between the first output node and a low-potential voltage line.