Apparatus, systems, and methods for dynamically reconfigured semiconductor tester for volatile and non-volatile memories

Abstract

A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of processing one or more firmware with or without operating system (i.e. bare-metal, embedded OS, RTOS (real time operating system)) to perform a series of task defined by firmware(s) for testing volatile and/or non-volatile memory devices connected into one or more DUT devices plus SCU has capability of having operating system and install and run host applications locally within each SCU units to mimic host applications environments along with performing regular memory testing.

Dependencies are inferred from the claim text.