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US 2024/0193017 A1Published application
Optimizing intermediate output accumulation of parallel processing operations in streaming and latency-sensitive applications
AssigneeNVIDIA Corporation
InventorDominik Wachowicz
Life of this patent
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Abstract
Disclosed are apparatuses, systems, and techniques for efficient parallel execution of multiple processes in real-time streaming and latency-sensitive applications. The techniques include but are not limited to executing in parallel multiple processing threads, storing data output by the multiple processing threads in respective accumulation buffers, and applying an aggregation function to the stored data to generate an aggregated data.
Claims20
A method comprising:
- executing, using a graphics processing unit (GPU), a first set of GPU threads to generate a first data for an application, wherein the first data is associated with a destination address of an output buffer;
- executing, using the GPU, a second set of GPU threads to generate a second data for the application, wherein the second data is associated with the destination address of the output buffer, and wherein the second set of GPU threads is executed concurrently with the first set of GPU threads;
- storing the first data in a first accumulation buffer;
- storing the second data in a second accumulation buffer;
- applying an aggregation function to the first data and the second data to generate an aggregated data;
- and
- storing the aggregated data at the destination address of the output buffer.
4 more elements
A system comprising:
- a memory device;
- a central processing unit (CPU) to:
- receive one or more calls from an application programming interface (API) of an application;
- and
- in response to the one or more calls from the API, schedule execution of a first set of threads and a second set of threads;
- a graphics processing unit (GPU) communicatively coupled to the memory device and to the CPU, the GPU to:
- execute the first set of threads to generate a first data for the application, wherein the first data is associated with a destination address in an output buffer of the memory device;
- execute a second set of threads to generate a second data for the application, wherein the second data is associated with the destination address in the output buffer of the memory device, and wherein the second set of threads is executed concurrently with the first set of threads;
- store the first data in a first accumulation buffer of the memory device;
- store the second data in a second accumulation buffer of the memory device;
- apply an aggregation function to the first data and the second data to generate an aggregated data;
- and
- store the aggregated data at the destination address in the output buffer of the memory device.
10 more elements
A parallel processor comprising:
- one or more memory buffers;
- and
- one or more processing cores communicatively coupled to the one or more memory buffers, the one or more processing cores to:
- execute a first set of one or more threads to generate a first data for an application, wherein the first data is associated with a destination address in an output buffer of the one or more memory buffers;
- execute a second set of one or more threads to generate a second data for the application, wherein the second data is associated with the destination address in the output buffer, and wherein the second set of threads is executed concurrently with the first set of threads;
- store the first data in a first accumulation buffer of the one or more memory buffers;
- store the second data in a second accumulation buffer of the one or more memory buffers;
- apply an aggregation function to the first data and the second data to generate an aggregated data;
- and
- store the aggregated data at the destination address in the output buffer.
7 more elements
Dependencies are inferred from the claim text.