Exitless guest to host notification

A method comprising:

• translating a single instruction from a first instruction set architecture into one or more instructions of a second instruction set architecture, the single instruction to include a field for an opcode;
• decoding the one or more instructions of the second instruction set architecture;
• and
• processing the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a physical or virtual processor.

A system comprising:

• a first processor core including:
• decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode;
• and
• execution processing resources to execute the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a second processor core;
• and
• memory coupled to the processor core to store the single instruction.