Phase shifted clock generator

An integrated circuit (IC), comprising:

• a phase shifted clock generator, comprising:
• a delay circuit comprising (i) a plurality of series-coupled inverters configured to receive a reference clock signal and generate a first phase shifted clock signal and (ii) a plurality of transistors coupled to the plurality of series-coupled inverters, wherein a phase difference between the first phase shifted clock signal and the reference clock signal is controlled based on a delay associated with each transistor;
• a first capacitor;
• a control circuit that is coupled to the first capacitor, and configured to control, based on the first phase shifted clock signal and the reference clock signal, a first control voltage generated at the first capacitor by at least one of a group consisting of charging and discharging the first capacitor, wherein the delay associated with each transistor of the plurality of transistors is controlled based on a magnitude of a second control voltage that is derived from the first control voltage;
• and
• a switch that is coupled to the first capacitor and the delay circuit, wherein when the control circuit is controlling the first control voltage, the switch is deactivated and the magnitude of the second control voltage is retained, and when the first capacitor retains an associated charge, the switch is activated and the magnitude of the second control voltage is equivalent to a magnitude of the first control voltage, and wherein the delay associated with each transistor is controlled such that the phase difference between the first phase shifted clock signal and the reference clock signal is within a predefined range.