Integrated circuit device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorGangjun KIM
Life of this patent
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Abstract
An integrated circuit device includes a substrate including an element isolation film defining an active area, and a gate structure buried in the active area of the substrate. The gate structure includes a gate trench, an outer insulating layer conformed along an inner wall of the gate trench, a channel structure layer conformed on the outer insulating layer, a gate insulating layer conformed on the channel structure layer, a gate electrode layer filling a lower area of the gate trench, and a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench.
Claims20
An integrated circuit device comprising:
- a substrate including an element isolation film defining an active area;
- and
- a gate structure buried in the active area of the substrate,
- the gate structure including
- a gate trench,
- an outer insulating layer formed conformally along an inner wall of the gate trench,
- a channel structure layer formed conformally on the outer insulating layer,
- a gate insulating layer formed conformally on the channel structure layer,
- a gate electrode layer filling a lower area of the gate trench, and
- a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench.
An integrated circuit device comprising:
- a substrate;
- a peripheral circuit structure on the substrate, the peripheral circuit structure including a peripheral circuit;
- a memory cell structure on the peripheral circuit structure, the memory cell structure including an element isolation film defining an active area;
- and
- a plurality of gate structures buried in the active area of the memory cell structure,
- each of the plurality of gate structures including
- a gate trench,
- an outer insulating layer formed conformally along an inner wall of the gate trench,
- a channel structure layer formed conformally on the outer insulating layer,
- a gate insulating layer formed conformally on the channel structure layer,
- a gate electrode layer filling a lower area of the gate trench, and
- a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench, and at least a portion of the plurality of gate structures electrically connected to the peripheral circuit through a vertical via.
An integrated circuit device comprising:
- a first structure;
- and
- a second structure stacked on the first structure, the first structure including
- a first substrate,
- a peripheral circuit on the first substrate,
- a first insulating layer configured to cover the first substrate and the peripheral circuit, and
- a first bonding pad on the first insulating layer and electrically connected to the peripheral circuit,
- the second structure including
- a second substrate facing the first substrate,
- a plurality of gate structures buried in an active area of the second substrate,
- a second insulating layer covering the second substrate and the plurality of gate structures, and
- a second bonding pad on the second insulating layer and electrically connected to at least one of the plurality of gate structures,
- each of the plurality of gate structures including
- a gate trench,
- an outer insulating layer formed conformally along an inner wall of the gate trench,
- a channel structure layer formed conformally on the outer insulating layer,
- a gate insulating layer formed conformally on the channel structure layer,
- a gate electrode layer filling a lower area of the gate trench, and
- a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench, and the first bonding pad and the second bonding pad bonded to each other.
Dependencies are inferred from the claim text.