Clock recovery with loop delay cancellation

A clock recovery method that comprises, in an integrated receiver circuit:

• sampling an analog receive signal in accordance with a sampling signal to obtain a digital receive signal;
• producing a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
• controlling a sampling signal phase via a first feedback path to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error;
• and
• buffering the sampling signal phase to reduce a magnitude of the residual phase error.

A nontransient information storage medium that comprises semiconductor manufacturing process mask patterns to make an integrated receiver circuit including:

• a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal;
• a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
• a first feedback path that controls a sampling signal phase to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error;
• and
• a loop-delay cancellation circuit that buffers the sampling signal phase to reduce the residual phase error.