Gate-all-around devices with different gate oxide thicknesses

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the first semiconductor region, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure;
• and
• a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the second semiconductor region, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure;
• wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer.

An integrated circuit comprising:

• a first semiconductor device having a plurality of first semiconductor nanoribbons extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the plurality of first semiconductor nanoribbons, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure;
• and
• a second semiconductor device having a plurality of second semiconductor nanoribbons extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the plurality of second semiconductor nanoribbons, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure;
• wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is thicker than the second gate oxide layer, and wherein the nanoribbons of the plurality of first semiconductor nanoribbons have a greater midpoint thickness compared to a midpoint thickness of the nanoribbons of the plurality of second semiconductor nanoribbons.