Recessed gate for an mv device

A semiconductor device, comprising:

• a first source/drain region and a second source/drain region in a substrate;
• a conductive gate inset into a top of the substrate, laterally between the first source/drain region and the second source/drain region;
• a gate dielectric layer separating the conductive gate from the substrate;
• a sidewall spacer overlying a top surface of the gate dielectric layer and on a sidewall of the conductive gate;
• and
• a first source/drain extension region underlying the first source/drain region and the conductive gate, wherein the first source/drain extension region is closer to a first bottom-surface portion of the substrate directly under the conductive gate than to a second bottom-surface portion of the substrate directly under the first source/drain region.

A semiconductor device, comprising:

• a first source/drain region and a second source/drain region in a substrate;
• a conductive gate inset into the substrate, laterally between the first source/drain region and the second source/drain region;
• a gate dielectric layer separating the conductive gate from the substrate and having a sidewall facing away from the conductive gate towards the first source/drain region;
• and
• a sidewall spacer overlying and directly contacting a top edge of the sidewall of the gate dielectric layer and on a sidewall of the conductive gate, wherein the top edge is laterally offset from sidewalls of the sidewall spacer.