Three-dimensional memory devices and fabricating methods thereof

A memory device, comprising:

• a first semiconductor structure, comprising:
• a first transistor comprising a first gate dielectric layer;
• a first semiconductor layer disposed on the first transistor;
• and
• a second transistor disposed on the first semiconductor layer, wherein the second transistor comprises a second gate dielectric layer having a thickness less than a thickness of the first gate dielectric layer;
• and
• a second semiconductor structure disposed on the first semiconductor structure, wherein the second semiconductor structure comprises memory cells coupled to the first transistor and the second transistor.

A storage system, comprising:

• a memory controller;
• and
• a memory device, comprising:
• a first semiconductor structure, comprising:
• a first set of peripheral circuits configured to operate with a first voltage;
• and
• a second set of peripheral circuits configured to operate with a second voltage lower than the first voltage, wherein the second set of peripheral circuits are disposed over the first set of peripheral circuits;
• and
• a second semiconductor structure disposed on the first semiconductor structure, wherein the second semiconductor structure comprises memory cells coupled to the first semiconductor structure.