Phase-locked loop reference clock management
OwnerAnkit Garg, Abhijit Patkiinventors
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Abstract
A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.
Claims20
A device, comprising:
- a phase-locked loop (PLL) having a reference input;
- a storage element;
- and
- a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider, the reference clock generator coupled to the storage element, the reference clock output coupled to the reference input, and the reference clock generator configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of a first clock signal at the reference clock output remains unchanged when a frequency of a second clock signal at the interface clock input changes.
A system, comprising:
- a first device having a data/control output and a clock output, the first device configured to provide control information of interface frames on the data/control output and to provide a variable frequency interface clock on the clock output;
- and
- a second device having a data/control input and a clock input, the data/control input coupled to the data/control output and the clock input coupled to the clock output, the second device having a phase-locked loop (PLL) having a PLL reference input, and the second device configured to generate a constant frequency PLL reference clock for the PLL reference input based on the variable frequency interface clock.
A method, comprising:
- receiving an interface clock at a first frequency;
- receiving a first value into a storage element;
- determining a first divide ratio for the interface clock at the first frequency based on the first value;
- dividing the interface clock's first frequency by the first divide ratio to produce a reference clock for a phase-locked loop (PLL);
- receiving a second value into the storage element;
- determining a second divide ratio for the interface clock at the second frequency based on the second value;
- receiving the interface clock at a second frequency;
- and
- dividing the interface clock's second frequency by the second divide ratio to produce the reference clock for the phase-locked loop (PLL), such that a frequency of the reference clock remains the same despite the change in the frequency of the interface clock.
Dependencies are inferred from the claim text.