Iec protection of high-frequency terminals

A method of electrostatic discharge, comprising;

• receiving a charge at a terminal of an integrated circuit from an electrostatic shock;
• conducting the charge from the terminal through a diode to a voltage node to pulse a voltage of the voltage node;
• and
• coupling the voltage node to a gate of a pass transistor having a drain coupled to the terminal in response to a detection of the pulse of the voltage of the voltage node.

An electrostatic discharge (ESD) circuit, comprising:

• an integrated circuit terminal;
• a node for a high-speed data signal;
• a pass transistor coupled between the node for the high-speed data signal and the integrated circuit terminal;
• and
• an ESD trigger circuit configured to couple a power supply node for a power supply voltage to a gate of the pass transistor in response to a positive electrostatic shock to the integrated circuit terminal.

An electrostatic discharge (ESD) circuit, comprising:

• an integrated circuit terminal;
• a node for a high-speed data signal;
• a pass transistor coupled between the node for the high-speed data signal and the integrated circuit terminal;
• and
• an ESD trigger circuit configured to couple a negative voltage node for a negative voltage to a gate of the pass transistor in response to a negative electrostatic shock to the integrated circuit terminal.