US 2024/0178323 A1 · INSULATING FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Abstract

In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.

Claims5

Dependent claims

A method for manufacturing a semiconductor device, comprising the steps of:

forming a plurality of first transistors having a channel formation region comprising silicon on a substrate;
forming a transistor having a channel formation region comprising an oxide semiconductor layer over the plurality of first transistors;
and
holding the substrate placed in a treatment chamber at a first temperature, introducing a source gas into the treatment chamber, and supplying a high-frequency power to an electrode in the treatment chamber so that an insulating film is formed over the transistor having the channel formation region comprising the oxide semiconductor layer,
wherein the first temperature is higher than or equal to 180° C. and lower than or equal to 260° C.,
wherein a pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa when the source gas is introduced, and
wherein the high-frequency power is higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2.

4 more elements

A semiconductor device comprising:

a first transistor having a first channel formation region comprising silicon;
a second transistor having a second channel formation region comprising silicon;
a third transistor having a third channel formation region comprising silicon;
a fourth transistor having a fourth channel formation region provided in an oxide semiconductor layer;
a first conductive layer over the first channel formation region;
a second conductive layer over the second channel formation region;
a third conductive layer over the third channel formation region;
a first insulating layer over the first conductive layer, the second conductive layer, and the third conductive layer;
a fourth conductive layer over and in contact with a top surface of the first insulating layer;
a second insulating layer over the fourth conductive layer;
the oxide semiconductor layer having a region being in contact with a top surface of the second insulating layer;
a third insulating layer over the oxide semiconductor layer;
a fifth conductive layer over the third insulating layer;
a fourth insulating layer over the fifth conductive layer;
a sixth conductive layer over the fourth insulating layer;
and
a seventh conductive layer over the fourth insulating layer,
wherein the first conductive layer has a region configured to be a gate electrode of the first transistor,
wherein the second conductive layer has a region configured to be a gate electrode of the second transistor,
wherein the third conductive layer has a region configured to be a gate electrode of the third transistor,
wherein the fourth conductive layer has a region configured to be a first gate electrode of the fourth transistor,
wherein the fifth conductive layer has a region configured to be a second gate electrode of the fourth transistor,
wherein the sixth conductive layer is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor,
wherein the seventh conductive layer is electrically connected to the other of the source and the drain of the fourth transistor,
wherein the seventh conductive layer has a first region overlapping with the third conductive layer and a second region overlapping with the fourth conductive layer, and
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor.

23 more elements

A semiconductor device comprising:

a first transistor having a first channel formation region comprising silicon;
a second transistor having a second channel formation region comprising silicon;
a third transistor having a third channel formation region comprising silicon;
a fourth transistor having a fourth channel formation region provided in an oxide semiconductor layer;
a first conductive layer over the first channel formation region;
a second conductive layer over the second channel formation region;
a third conductive layer over the third channel formation region;
a first insulating layer over the first conductive layer, the second conductive layer, and the third conductive layer;
a fourth conductive layer over and in contact with a top surface of the first insulating layer;
a second insulating layer over the fourth conductive layer;
the oxide semiconductor layer having a region being in contact with a top surface of the second insulating layer;
a third insulating layer over the oxide semiconductor layer;
a fifth conductive layer over the third insulating layer;
a fourth insulating layer over the fifth conductive layer;
a sixth conductive layer over the fourth insulating layer;
and
a seventh conductive layer over the fourth insulating layer,
wherein the first conductive layer has a region configured to be a gate electrode of the first transistor,
wherein the second conductive layer has a region configured to be a gate electrode of the second transistor,
wherein the third conductive layer has a region configured to be a gate electrode of the third transistor,
wherein the fourth conductive layer has a region configured to be a first gate electrode of the fourth transistor,
wherein the fifth conductive layer has a region configured to be a second gate electrode of the fourth transistor,
wherein the sixth conductive layer is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor,
wherein the seventh conductive layer is electrically connected to the other of the source and the drain of the fourth transistor,
wherein the seventh conductive layer has a first region overlapping with the third conductive layer and a second region overlapping with the fourth conductive layer,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, and
wherein the first transistor and the second transistor are p-channel transistors.

24 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/433,864Filed 6 Feb 2024

Priority

JP 2012-0874326 Apr 2012

Published

30 May 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 30/031
Of FETs having insulated gates [IGFET]: of thin-film transistors [TFT]
H10D 30/6704
Thin-film transistors [TFT]: having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling…
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Family

Application13/795,770Continuation · filed 12 Mar 2013

Application14/543,287Continuation · filed 17 Nov 2014

Application15/071,700Continuation · filed 16 Mar 2016

Application15/401,460Continuation · filed 9 Jan 2017

Application16/123,406Continuation · filed 6 Sep 2018

Application16/986,387Continuation · filed 6 Aug 2020

Application17/900,955Division · filed 1 Sep 2022

Application18/433,864Division

Application17/900,955Continuation

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