Chip package and method for forming the same

A chip package, comprising:

• a substrate and a capping layer, successively stacked on a package substrate;
• a dam structure sandwiched between the substrate and the capping layer and surrounding a sensing region in the substrate;
• an encapsulant layer formed on the package substrate and surrounding the substrate, the dam structure and the capping layer;
• and
• an adhesive layer formed between a lower portion of the dam structure and the encapsulant layer;
• wherein a bottom width of the substrate is greater than a top width of the substrate;
• wherein a first interface between the capping layer and the encapsulant layer and a second interface between the encapsulant layer and an upper portion of the dam structure are substantially aligned with each other and extend in the same direction;
• and
• wherein the encapsulant layer has a rounded angle in direct contact with the adhesive layer.

A method for forming a chip package, comprising:

• bonding a transparent substrate to a carrier substrate via a tape layer, wherein the transparent substrate has a first region and a second region surrounding the first region;
• forming a dam structure on the transparent substrate, wherein the dam structure extends along an edge of the first region to surround the first region;
• performing a first dicing process to partially remove the dam structure and form an opening in the transparent substrate, wherein the opening surrounds the first region and exposes the tape layer;
• bonding a substrate to the transparent substrate, wherein the substrate has a chip region corresponding to the first region and a scribe-line region corresponding to the second region;
• performing a debonding process to remove the tape layer, the carrier substrate, and a portion of the transparent substrate, so that a remaining transparent substrate forms a capping layer over the substrate and exposes the scribe-line region;
• and
• performing a second dicing process on the exposed scribe-line region, so that the substrate of the chip region forms a stepped sidewall.