Array substrate and manufacturing method thereof, and display panel

A manufacturing method of an array substrate, comprising following steps:

• S1, providing a substrate, and manufacturing an oxide semiconductor layer on the substrate;
• S2, manufacturing a gate insulating layer, a gate electrode, and an interlayer insulating layer on the oxide semiconductor layer, and forming a channel region and conductive regions located at both sides of the channel region;
• S3, forming via holes penetrating the interlayer insulating layer and exposing the conductive regions;
• and
• S4, manufacturing a source-drain electrode metal layer on the interlayer insulating layer, wherein the source-drain electrode metal layer is electrically connected to the conductive regions through the via holes;
• wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate.

A display panel, comprising an array substrate and an opposed substrate, the array substrate and the opposed substrate disposed opposite to each other, wherein the array substrate comprises:

• a substrate;
• an oxide semiconductor layer disposed on the substrate, comprising a channel region and conductive regions located at both sides of the channel region;
• a gate insulating layer disposed on a side of the oxide semiconductor layer away from the substrate;
• a gate electrode disposed on a side of the gate insulating layer away from the substrate;
• an interlayer insulating layer disposed on a side of the gate electrode away from the substrate;
• and
• a source-drain electrode metal layer disposed on a side of the interlayer insulating layer away from the substrate, and electrically connected to the conductive regions through via holes penetrating the interlayer insulating layer;
• wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate.