Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a lower redistribution wiring layer having first redistribution wirings stacked in at least two layers;
• a semiconductor chip on the lower redistribution wiring layer, the semiconductor chip having a first surface with chip pads on the first surface, and the first surface facing the lower redistribution wiring layer;
• a sealing member covering the semiconductor chip on the lower redistribution wiring layer;
• a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings;
• and
• an upper redistribution wiring layer on the sealing member,
• wherein each of the first redistribution wirings includes a barrier layer pattern, a seed layer pattern and a plating pattern sequentially stacked on one another, and
• viewed from a plan view, a sidewall of the barrier layer pattern extends laterally beyond a sidewall of the seed layer pattern.

A semiconductor package, comprising:

• a lower redistribution wiring layer having first redistribution wirings stacked in at least two layers;
• a semiconductor chip on the lower redistribution wiring layer and electrically connected to the first redistribution wirings;
• a sealing member covering the semiconductor chip on the lower redistribution wiring layer;
• a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings;
• and
• an upper redistribution wiring layer on the sealing member,
• wherein each of the first redistribution wirings includes a redistribution via penetrating an underlying insulating layer, a redistribution pad on the redistribution via, and a redistribution line extending from the redistribution pad on the underlying insulating layer,
• wherein the redistribution line includes a barrier layer pattern, a seed layer pattern and a plating pattern sequentially stacked on the underlying insulating layer, and
• wherein the redistribution line includes a recess configured by a sidewall of the seed layer pattern recessed from a sidewall of the plating pattern and a sidewall of the barrier layer pattern.