Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device

A chip stacked structure, comprising:

• a first chip comprising:
• a first, substrate;
• a first functional layer disposed on the first substrate;
• and
• first through silicon vias that penetrate the first substrate and the first functional layer, wherein each of the first through silicon vias comprises:
• an electroplated column comprising a side surface and a first surface;
• and
• a first conductive barrier layer wrapping the side surface and not disposed on the first surface;
• a second chip located away from the first surface and comprising:
• a second substrate;
• and
• a second functional layer disposed on the second substrate and comprising a first side located away from the second substrate;
• a first redistribution layer disposed on the first side;
• a first dielectric layer disposed between the first substrate and the first redistribution layer;
• and
• a plurality of first bonding metal blocks disposed in the first dielectric layer,
• wherein at least some of the first bonding metal blocks are electrically coupled to the first through silicon vias and the first redistribution layer, and
• wherein the first chip and the second chip are bonded through the first dielectric layer and the first bonding metal blocks.

An electronic device, comprising:

• a printed circuit board;
• and
• a chip stacked structure electrically coupled to the printed circuit board and comprising:
• a first chip comprising:
• a first substrate;
• a first functional layer disposed on the first substrate;
• and
• first through silicon vias that penetrate the first substrate and the first functional layer, wherein a first diameter of the first through silicon via close to the first functional layer is greater than a second diameter of the first through silicon via close to the first substrate;
• a second chip comprising:
• a second substrate;
• and
• a second functional layer disposed on the second substrate and comprising a first side located away from the second substrate;
• a first redistribution layer disposed on the first side;
• a first dielectric layer disposed between the first substrate and the first redistribution layer;
• and
• a plurality of first bonding metal blocks disposed in the first dielectric layer,
• wherein at least some of the first bonding metal blocks are electrically coupled to the first through silicon vias and the first redistribution layer, and
• wherein the first chip and the second chip are bonded through the first dielectric layer and the first bonding metal blocks.

A manufacturing method, comprising:

• forming first through silicon vias on a first chip from a first side of a first functional layer of the first chip;
• bonding a carrier and the first chip, so that the first functional layer is closer to the carrier than a first substrate of the first chip;
• forming a first redistribution layer on a second functional layer of a second chip;
• bonding the first chip and the second chip;
• forming a first dielectric layer between the first substrate and the first redistribution layer;
• and
• forming a plurality of first bonding metal blocks located in the first dielectric layer, wherein so that at least some of the first bonding metal blocks are electrically connected to the first through silicon vias and the first redistribution layer.