Semiconductor processing device and semiconductor processing system

A semiconductor processing device comprising:

• a wafer transfer robot including a hand unit for gripping a wafer and a driving unit connected to the hand unit for moving the wafer;
• an aligner including a stage on which the wafer is seated, a camera sensor installed above the stage to image a partial region of the wafer at a time, and a laser sensor installed above the stage to measure a distance to a surface of the wafer;
• and
• a controller configured to control the wafer transfer robot and the aligner,
• wherein the controller is configured such that, when the wafer is seated on the stage:
• the controller acquires a plurality of sub-images of a partial region of the wafer captured by the camera sensor, while rotating the wafer using the stage, and determines a surface defect of the wafer using the plurality of sub-images, and
• the controller determines a curve defect of the wafer based on a distance to a surface of the wafer measured by the laser sensor, while rotating the wafer using the stage.

A semiconductor processing device comprising:

• at least one process chamber configured to perform a semiconductor process on a wafer;
• a wafer transfer robot configured to move the wafer transferred by a front open unified pod (FOUP);
• an aligner configured to receive the wafer from the wafer transfer robot and rotate the wafer to align the wafer in a predetermined direction;
• and
• a load-lock chamber configured to transfer the wafer between the process chamber and the wafer transfer robot,
• wherein the aligner includes a stage for rotating the wafer, an aligning sensor mounted above the stage and configured to recognize a notch or a flat zone of the wafer, a lighting device mounted above the stage and configured to irradiate a partial region of the wafer with light, a camera sensor mounted above the stage and configured to image a partial region of the wafer, and a laser sensor mounted above the stage and configured to measure a distance to an upper surface of the wafer.