Wafer dicing method and method of manufacturing semiconductor device by using the same

A method of manufacturing a semiconductor device, the method comprising:

• preparing a wafer having a plurality of device formation areas and a scribe lane area between the plurality of device formation areas;
• forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer;
• forming a plurality of insulating layers and a wiring layer on the wafer;
• forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction;
• forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves;
• forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves;
• separating the plurality of semiconductor devices from each other along the one or more internal cracks;
• and
• packaging each of the plurality of semiconductor devices responsive to the separating,
• wherein the plurality of first grooves pass through at least one of the plurality of insulating layers and the wiring layer in the vertical direction.

A method of manufacturing a semiconductor device, the method comprising:

• preparing a plurality of device formation areas and a scribe lane area between the plurality of device formation areas;
• forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer;
• forming a plurality of insulating layers and a wiring layer on the wafer;
• forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction;
• forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves;
• forming one or more internal cracks in the wafer by irradiating the scribe lane area with a laser beam along lower surfaces of the plurality of second grooves;
• separating the plurality of semiconductor devices from each other along the one or more internal cracks;
• and
• packaging each of the plurality of semiconductor devices responsive to the separating,
• wherein the forming of the plurality of first grooves in the scribe lane area comprises performing at least one of a laser etching method using a first laser device, and a plasma etching method,
• the planarizing of the lower surfaces of the plurality of first grooves comprises performing at least one of a laser etching method using a second laser device, and a chemical mechanical polish (CMP) method,
• the forming of the one or more internal cracks comprises performing a laser etching method using a third laser device, and
• the plurality of first grooves pass through at least one of the plurality of insulating layers and the wiring layer in the vertical direction.