Solid-state switch based high-speed pulser with plasma iedf modification capability through multilevel output functionality

A method for etching using a pulsed waveform, comprising:

• generating a plasma in a chamber body;
• applying a pulsed DC voltage to the plasma using a bias electrode capacitively coupled to the plasma through a dielectric layer, wherein the pulsed DC voltage comprises a plurality of pulses, each of the plurality of pulses further comprising a plurality of signals, and wherein each of the plurality of signals has an off-time, a pulse width, and an amplitude;
• and
• etching a substrate in the chamber body using the pulsed DC voltage applied to the plasma.

A pulsed signal source device for etching, comprising:

• a controller;
• a bias electrode;
• and
• a bias voltage source configured to supply a pulsed biasing voltage to the bias electrode, the bias voltage source comprising:
• a DC voltage source;
• a first capacitor connected in series with the DC voltage source;
• a first diode connected with the first capacitor;
• a ground connected in series with the first diode;
• a first resistor connected in parallel with the first capacitor;
• a first metal oxide semiconductor field effect transistor connected in series to the first resistor;
• a first gate voltage source connected to a gate terminal of the first metal oxide semiconductor field effect transistor;
• a second capacitor connected in series with between the first diode and ground;
• a second diode connected in series between the second capacitor and ground;
• a second resistor connected in parallel with the second capacitor;
• a second metal oxide semiconductor field effect transistor connected in series to the second resistor;
• a second gate voltage source connected to a gate terminal of the second metal oxide semiconductor field effect transistor;
• a second blocking diode connected to a source terminal of the second metal oxide semiconductor field effect transistor;
• a third capacitor connected in series with between the second diode and ground;
• a third resistor connected in parallel with the third capacitor;
• a third metal oxide semiconductor field effect transistor connected in series to the third resistor;
• a third gate voltage source connected to a gate terminal of the third metal oxide semiconductor field effect transistor;
• and
• a third blocking diode connected to a source terminal of the third metal oxide semiconductor field effect transistor.