Memory device performing multiplication using logical states of memory cells

An apparatus comprising:

• a memory cell array comprising memory cells, wherein each memory cell is programmable to store a respective bit for a multi-bit weight, and each memory cell has a position in the array corresponding to a significance of its stored respective bit;
• and
• a multiplier-accumulator unit configured to perform a multiplication of the multi-bit weight by a multi-bit input and provide an accumulation result, wherein:
• the memory cells are kept in a sub-threshold mode during the multiplication;
• each bit of the multi-bit input is applied to the multiplier-accumulator unit at a respective time instance to obtain a respective result, wherein the respective result is based on summing output currents from the memory cells;
• and
• the accumulation result is based on the respective results obtained from applying the bits of the multi-bit input.

An apparatus comprising:

• a memory cell array comprising memory cells, wherein each memory cell is programmable to store a respective bit for a multi-bit weight, and each memory cell has a position in the array corresponding to a significance of its stored respective bit;
• voltage drivers configured to apply voltage pulses to the memory cells, wherein a respective width of each pulse represents a multi-bit input;
• a first line coupled to first memory cells storing a bit of a first significance, wherein the first line is configured to collect first output currents from each of the first memory cells for accumulating a first charge;
• a second line coupled to second memory cells storing a bit of a second significance, wherein the second significance is less than the first significance, and the second line is configured to collect second output currents from each of the second memory cells for accumulating a second charge;
• and
• a logic circuit configured to output a result based on the accumulated first charge and the accumulated second charge.