Volatile data storage in nand memory

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a plurality of access lines, wherein each access line of the plurality of access lines is connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to cause to memory to:
• isolate a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells from a data line selectively connected to the particular string of series-connected memory cells;
• boost a voltage level of a channel material of the particular string of series-connected memory cells to have a boosted voltage level;
• and
• selectively discharge the boosted voltage level of the channel material of the particular string of series-connected memory cells to the data line in response to a desired data state of the particular string of series-connected memory cells.

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a plurality of access lines, wherein each access line of the plurality of access lines is connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller is configured to cause to memory to:
• isolate a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells from a common source;
• connect the particular string of series-connected memory cells to a data line selectively connected to the particular string of series-connected memory cells;
• activate each memory cell of the string of series-connected memory cells;
• and
• determine a data state of the particular string of series-connected memory cells in response to a voltage level of the data line.