Fault tolerant systems and methods using shared memory configurations

A fault tolerant computer system comprising:

• one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices;
• one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device;
• a first management processor in electrical communication with the cache coherent switch;
• a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes;
• and
• a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes,
• wherein data stored in the one or more shared memory complexes by the first compute node and modified thereby because of operations executing on the first compute node is available for the second compute node to use and modify on a substantially real time basis in the event the second compute node takes over for the first node upon the first compute node undergoing a performance degradation event.