Operating methods, memory controllers, and memory systems
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsJin Cai, Xianwu Luo
Life of this patent
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Abstract
The present application discloses example operating methods for memory controllers, memory controllers, systems, and electronic devices. The operating methods include: in response to a working mode switching command, determining a state of redundancy check data in a redundancy check cache of a memory controller, and the redundancy check data being used for data recovery of a corresponding storage area in a memory array; and backing up the redundancy check data in the state of an updated state into a backup area of the memory array. Other examples are described.
Claims20
An operating method for a memory controller contained in a memory system, the memory system further includes a memory, and the memory includes a memory array and is controlled by the memory controller;
- the operating method comprising:
- in response to a working mode switching command, determining a state of redundancy check data in a redundancy check cache of the memory controller, the redundancy check data being used for data recovery of a corresponding storage area in the memory array;
- and
- backing up the redundancy check data in the state of an updated state into a backup area of the memory array.
A memory controller, wherein the memory controller is contained in a memory system, the memory system further comprises a memory, and the memory comprises a memory array and is controlled by the memory controller;
- the memory controller comprises a processor and a redundancy check cache, wherein, the processor is configured to at least:
- in response to a working mode switching command, determine a state of redundancy check data in the redundancy check cache of the memory controller, the redundancy check data being used for data recovery of a storage area of a corresponding state in the memory array;
- and
- back up the redundancy check data in the state of an updated state into a backup area of the memory array.
A memory system, comprising:
- one or more memories including a memory array;
- and
- a memory controller coupled with the one or more memories and configured to control the one or more memories, wherein the memory controller includes:
- a first communication interface coupled with a host and configured to receive a working mode switching command sent by the host;
- a redundancy check cache;
- a processor configured to at least:
- in response to the working mode switching command, determine a state of each redundancy check data in the redundancy check cache, each redundancy check data being used for fault data recovery of a corresponding storage area in the memory array;
- and
- generate a write command carrying the redundancy check cache in the state of an updated state;
- and
- a second communication interface coupled with the one or more memories and configured to at least:
- send the write command to the one or more memories;
- wherein the one or more memories are configured to at least:
- in response to the write command, write the redundancy check data in the state of the updated state into a backup area of the memory array.
Dependencies are inferred from the claim text.