Storage device for reducing reliability degradation of os data through stage change before smt process and method for operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJun-Ho SEO, Seongyong KIM
Life of this patent
Estimating the term…
Abstract
A method of operating a storage device for programming data into a flash memory before a surface mount technology (SMT) process is provided. The method includes: comparing program states of first memory cells connected to a first word line with program states of second memory cells connected to a second word line; changing the program states of the second memory cells according to a result of the comparing; and multi-bit programming the data and changed state information into the second memory cells.
Claims20
A method of operating a storage device for programming data into a flash memory before a surface mount technology (SMT) process, the method comprising:
- comparing program states of first memory cells connected to a first word line with program states of second memory cells connected to a second word line;
- changing the program states of the second memory cells according to a result of the comparing;
- and
- multi-bit programming the data and changed state information into the second memory cells.
A method of operating a storage device for programming data into a flash memory before a surface mount technology (SMT) process, comprising:
- programming first memory cells connected to a first word line;
- reading first program states of the first memory cells;
- checking second program states of second memory cells connected to a second word line;
- comparing the first program states with the second program states;
- changing the second program states according to a result of the comparing;
- and
- multi-bit programming the data and changed state information into the second memory cells.
A storage device comprising:
- a flash memory comprising first memory cells connected to a first word line and second memory cells connected to a second word line;
- and
- a memory controller configured to compare program states of the first memory cells with program states of the second memory cells, change the program states of the second memory cells according to a comparison result, and multi-bit program data and changed state information into the second memory cells.
Dependencies are inferred from the claim text.