Array substrate, method for manufacturing array substrate, and display panel

A method for manufacturing an array substrate, wherein the method comprises:

• providing a substrate;
• forming a gate electrode, a gate insulating layer, and a first semiconductor on the substrate;
• wherein the gate insulating layer covers the gate electrode, and the gate insulating layer is located between the gate electrode and the first semiconductor;
• forming a second semiconductor at both opposite ends of the first semiconductor respectively, and forming an active layer by making the two second semiconductors in contact with two ends of the first semiconductor respectively;
• the first semiconductor layer is one of an N-type semiconductor and a P-type semiconductor, and the second semiconductor layer is other one of the P-type semiconductor and the N-type semiconductor;
• forming a source drain layer on the active layer and electrically connecting a source electrode and a drain electrode of the source drain layer with the two second semiconductors respectively.

A display panel, wherein the display panel comprises an array substrate and an opposite substrate, and the array substrate is arranged at an interval relative with the opposite substrate;

• the array substrate comprises a substrate and a driving transistor layer formed on the substrate;
• wherein the driving transistor layer comprises at least one driving transistor, each of the driving transistors comprise:
• a gate electrode;
• an active layer arranged opposite to a position of the gate electrode, the active layer comprising a first semiconductor and two second semiconductors, the two second semiconductors are arranged at opposite ends of the first semiconductor and are respectively in contact with the first semiconductor to form a first PN junction and a second PN junction, and a conduction direction of the first PN junction and a conduction direction of the second PN junction are inverse;
• and
• a source drain layer arranged opposite to a position of the active layer, the source drain layer comprising a source electrode and a drain electrode, the source electrode is connected with the second semiconductor at a position of the first PN junction, and the drain electrode being connected with the second semiconductor at a position of the second PN junction.