US 2024/0154607 A1 · MANAGING SIGNAL TRANSFERS IN SEMICONDUCTOR DEVICES

Abstract

Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.

Claims20

Dependent claims

An integrated circuit, comprising:

one or more target units each configured to receive a signal comprising an initial rising edge and an initial falling edge;
and
a plurality of inverting units arranged on signal paths to the one or more target units,
wherein, for each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to compensate a difference between a rising delay time and a falling delay time associated with the signal along the corresponding signal path to cause a difference between a signal width of a multi-inverted signal received by the target unit and a signal width of the signal to be smaller than a predetermined threshold.

1 more element

A semiconductor device comprising:

a first integrated circuit configured to store data;
and
a second integrated circuit coupled to the first integrated circuit,
wherein the first integrated circuit comprises:
one or more data units each configured to receive a signal comprising an initial rising edge and an initial falling edge;
and
a plurality of inverting units arranged on signal paths to the one or more data units,
wherein, for each of the one or more data units, one or more corresponding inverting units the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the data unit to compensate a difference between a rising delay time and a falling delay time associated with the signal along the corresponding signal path to cause a difference between a signal width of a multi-inverted signal received by the data unit and a signal width of the signal to be smaller than a predetermined threshold, and
wherein the first integrated circuit is configured to transfer the data from the one or more data units to the second integrated circuit according to corresponding signals received by the one or more data units.

6 more elements

A method comprising:

transmitting a signal to each of one or more data units through a signal bus that is coupled to each of the one or more data units, the signal comprising an initial rising edge and an initial falling edge;
inverting, for each of the one or more data units, the signal multiple times along a corresponding signal path to the data unit to compensate a difference between a rising delay time and a falling delay time associated with the signal along the corresponding signal path to cause a difference between a signal width of a multi-inverted signal received by the data unit and a signal width of the signal before the signal is transmitted to be smaller than a predetermined threshold, wherein the corresponding signal path comprises at least a part of the signal bus;
and
transferring data stored in the one or more data units according to corresponding signals received by the one or more data units.

1 more element

Dependencies are inferred from the claim text.

Managing signal transfers in semiconductor devices

Life of this patent

Managing signal transfers in semiconductor devices

Life of this patent

Abstract

Claims20